In a memory array of a memory macro, a global bit line is coupled with a plurality of local input-output circuits (LIOs). Each LIO is shared by a pair of an upper memory bank and a lower memory bank of a memory segment. Each LIO is also coupled with a pair of local bit lines, one upper local bit line from the upper memory bank and one lower local bit line from the lower memory bank. Each upper and lower local bit line of a memory segment is coupled with a plurality of memory cells. In some approaches, the upper local bit line and the lower local bit line are coupled together.
In some approaches, the global bit line is electrically shorted with a plurality of pairs of upper and lower local bit lines from corresponding memory banks and memory segments. To write data to a memory cell, the data travels through the global bit line, a corresponding LIO, and a corresponding pair of upper and lower local bit lines. Because the global bit line is shorted with the plurality of pairs of upper and lower local bit lines, however, the memory cell to be written is affected by an effective capacitance of the global bit line and of the plurality of pairs of upper and lower local bit lines. A large effective capacitance of the global bit line and/or of each upper and lower local bit line degrades writing speed of the memory cells.
Like reference symbols in the various drawings indicate like elements.